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technical data 2013, dece m ber , ver.0 4 cmos ic of real time watch with serial interface, 64 8 ram functions and features ? count of seconds, minutes , hours , week days , date , months and years with consideration of the leap years ( before 2100); ? 56 bytes of the power self - sufficient ram for the data storage ; ? two - wire consecutive interface; ? programmable rectangular output signal ; ? automatic determination of the supply voltage d r op and the switching diagram ; ? consumption of less than 500 n in the back - up supply mode with the operating generator ; ? temperature range of the industrial application : - 40 ? C ? 85 ? ? accuracy is better than 1 minute per mo nth ordering information d evice operating temperature range package packing i n1307n t a = - 40 c ~+ 85 c for all packages dip - 8 tube i n1307dt sop - 8 tape& reel i n1307d sop - 8 tube description IN1307 is essentially the binary C decimal digital watch with a calendar, it has the additional 56 bytes of the power self - sufficient static ram and possesses the low power consumption. the addresses and data are applied consecutively via the two - wire bi - d irectional bus. the microcircuit is intended for count of the real time in hours, minutes and seconds, count of week days, date, month and year. the last day of the month is automatically adjusted for the months of less, than 31 days, including correction for the leap year. the watches function in the 24 - hour format or in the 12 - hour format with the am / pm - indicator. IN1307 has the built - in power supply control circuit, which determines the supply disruption and automatically switches over the device into the battery mode. pin discription pin symbol i/o pin des cription 1 x 1 in pin for connection of the quartz resonator 2 x2 in pin for connection of the quartz resonator 3 vbat in pin for battery 4 gnd in ground pin 5 sda bi input / output of serial data 6 scl in input of the consecutive cycle signal 7 sqw/out out output of rectangular signal 8 vcc in power supply pin IN1307 sop - 8 dip - 8 t a = - 40 to+ 85 ? c for all packages
i n1307 2 2013, dece m ber , ver.0 4 block diagram operating temperatures range operating temperatures range of the microcircuit IN1307: = - 40 ... + 85 ? . recommended dc oper ati ng condition and absolute maximum rating parameter symbol recommended operati ng condition absolute maximum rating unit min max min max supply voltage v 4.5 5.5 - 0.5 7.0 v battery voltage v bat 2.0 3.5 - 0.5 7.0 v low level input voltage v il - 0.3 0.8 - 0.5 7.0 v high level input voltage v ih 2.2 v cc + 0.3 - 0.5 7.0 v storage temperature t s - - - 55 +125 ? * stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those ind i- cated under recommended oper ating conditions is not implied. exposure to absolute - maximum - rated conditions for extended periods may affect device reliability. g e n e r a t o r & d i v i d e r p u l s e f o r m e r c o n t r o l c i r c u i t s a d d r e s s r e g i s t e r s u p p l y c o n t r o l i n t e r f a c e b u s r t c r a m ( 5 6 x 8 ) s q w / o u t v c c v b a t g n d s c l s d a x 1 x 2
i n1307 3 2013, dece m ber , ver.0 4 dc electrical characteristics ( = C 40...+ 85 ? , v cc = 4.5 C 5.5 v ) parameter symbol mode limit unit min max input leakage current, (scl only ) i li C C 1 u in / out leakage current, (sda and sqw/out) i lo C C 1 u low level output voltage v ol 1) v = 4.5 v C 0.4 v consumption current in the data transfer mode i cca f scl = 100 khz C 1500 consumption current in the static mode i ccs v = 5 v and sda, scl = 5 v C 200 consumption current in the battery mode ( sqw / out off ., 32 khz C on ) i bat 1 v cc = 0 v, v bat = 3 v C 0.5 a consumption current in the battery mode ( sqw / out C on , 32 khz C on ) i bat 2 v cc = 0 v, v bat = 3 v C 0.8 a low level voltage is determined under the load current of 5 m ; v ol = gnd under the capacitance load ac electrical characteristics ( = C 40...+ 85 ? , v cc = 4.5 C 5.5 v ) parameter symbol mode limit unit min max cycle frequency scl f scl C 0 100 khz time of the bus vacant status between the statuses of stop and start t buf C 4.7 C s hold time ( repeated ) of start status t hd:sta 1) C 4.0 C s duration of the low status of the cycle pulse scl t low C 4.7 C s duration of the cycle pulse high status scl t high C 4.0 C s pre - set time for the repeated status start t su:sta C 4.7 C s data hold time t hd:dat 2) C 0 C s data pre - set time t su:dat C 250 C ns rise time of signals sda and scl t r C C 1000 ns drop time of signals sda and scl t f C C 3 00 ns pre - set time for the status stop t su:sto C 4.7 C us total capacitance load per each bus line c b C C 400 pf in / out capacitance c i/o C 10 10 pf load capacitance of the quartz resonator lx C 12.5 12.5 pf after this time interval the first time cycle signal is formed; device should internally ensure the hold time, at least, 300 nsec for the signal sda (relative to v ihmin of signal scl ) in order to overlap the indeterminancy area of the fall signal of scl. maximum value t hd:dat should be definite in that case, if the device does not increase duration of the low status (t low ) of signal scl.
i n1307 4 2013, dece m ber , ver.0 4 typical operation characteristics (vcc=5.0v, t a = +25 ? c, unless otherwise noted)
i n1307 5 2013, dece m ber , ver.0 4 timing chart functioning IN1307 operates as the driven device on the serial bus. for access to it it is required to set the status start and to send after the register address the device identification code. it is poss i- ble to address the next register consequently, until the status stop is set. when v cc drops below 1.25 x v bat , the access in progress to the device is ceased and the address counter is reset. at this time the device does not recognize the input data, excluding the erroneous information wr iting. when v cc drops below v bat , the device switches over to the battery mode, consuming low power. when switching on the power supply v cc above v bat + 0.2 v, the device switches over from the battery power supply to v cc ; and recognizes the input data, wh en v cc becomes above 1.25 x v bat . addresses chart of rtc and ram addresses chart of the registers rtc and ram is indicated in the figure. hour registers of the real time are positioned at the addresses 00h C 07h. ram registers are positioned at the a d- dresses of 08h C 3fh. in the mode of the multi - byte access, when reaching by the pointer of the address 3fh, the end of the ram address space, there happens transition to the register with the address 00h, beginning of the hours area.
i n1307 6 2013, dece m ber , ver.0 4 oscillator circ uit IN1307 uses an external 32.768khz crystal. the oscillator circuit does not require any exte r- nal resistors or capacitors to operate. table specifies several crystal parameters for the external crystal. crystal specifications * parameter symbol min typ max unit nominal frequency f o 32.768 khz series resistance esr 45 k ? l 12.5 pf *the crystal, traces, and crystal input pins should be isolated from rf generating signals. application note : crystal considerations for real - time clocks for additional specifications. see 12 page. clock accuracy the accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. additional error will be added by crystal frequency drift caused by temper a- ture shifts. externalcircuit noise coupled into the oscillator. oscillator circuit showing internal bias network . figure shows a func tional schematic of the oscillator circuit. if using a crystal with the specified characteristics, the startup time is usually less than one second.
i n1307 7 2013, dece m ber , ver.0 4 recommended layout for crystal hours and calendar information on the time and date is obtained by means of reading the appropriate register bytes. hour registers of the real time are indicated in the figure. pre - setting and time and calendar initialization are performed by means of writing the appropriate bytes. information, contained in the time and calendar registers, represents the binary - decimal code. bit 7 of register 0 represents the hour stop bit (ch). when this bit is set to 1 , the generator is off. when switching on the power supply, the initi al status of all registers is not determined. it is necessary to enable the generator (bit ch = 0) when setting the initial configurations. IN1307 operates in the 12 - hour or in the 24 - hour format. the bit 6 of the watch register d e- termines the operational mode. 12 - hour mode corresponds to the high level. in the 12 - hour mode the bit 5 is the am/pm bit. the high level corresponds to pm. in the 24 - hour mode, the 5 is the second bit of tens of hours (20 - 23 hours). during application of the signal start to th e two - wire bus there happens transfer of the real time to the auxiliary set of registers. the time data are read from these auxiliary registers, while the watch proceeds in operation. this eliminates the necessity of repeated reading in case of updating th e basic registers in the access process. registers rtc IN1307
i n1307 8 2013, dece m ber , ver.0 4 control register control register is used for control of pin sqw/out. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 out x x sqwe x x rs1 rs0 out (output control): this bit presets the output logic level of the pin sqw/out, when the output of the rectangular signal is locked. sqwe (rectangular signal enabling): this bit, pre - set to the logic 1, activates the generator output. frequency of the output rectangular signal is determined by the bits rs0 and rs1. rs (frequency selection): these bits determine the frequency of the output rectangular signal, when the output of the rectangular signal is activated. the table indicates the frequencies, which can be selected by the bi ts rs. rs1 rs0 frequency sqw/out 0 0 1 hz 0 1 4,096 khz 1 0 8,192 khz 1 1 32,768 ??
i n1307 9 2013, dece m ber , ver.0 4 two - wire serial data bus IN1307 supports the bi - directional two - wire bus and the protocol of the data exchange. the bus can be controlled by the master device, which generates the cycle signal (scl), controls a c- cess to the bus, generates the statuses start and stop. typical configuration of the bus with the two - wire protocol is indicated in figure. data transfer can be initiated only when the bus is not occupied. in the process of the data transfer the data line should remain stable, while the line of the cycle signal is in the high status. status alterations of the data line at that moment, when the cycle line is in the high status, will be regarded as t he control signals. in compliance with this the following conditions are determined: bus not occupied: both the data line and the cycle signal are in the high status. data transfer start: status alteration of the data line during transition from high to lo w, while the cycle line is in the high status, is determined as the status start. data transfer stop: status alteration of the data line during transition from low to high, while the cycle line is in the high status, is determined as the status stop. valid data: data line status complies with the valid data, when after the status start the data line is stable during the high status of the cycle signal. data on the line should be altered at the time of the low status of the cycle signal. one cycle pulse per one data bit. each data transfer starts at the beginning of the status start and ceases at the beginning of the status stop. number of the data bytes, transferred between the statuses start and stop is not limited and is determined by the ?master? device. information is transferred byte by byte, and each receipt is confirmed by the ninth byte. IN1307 operates in the normal mode only (100 khz). confirmation of receipt: each receiving device, when it being addressed, has to generate the recept confirmation af ter receiving each byte. ?master? device should generate the cycle pulses, which are allocated in compliance with the confirmation bits. if the receipt confirmation signal is in the high status, then on arrival of the confirmation cycle pulse, the device, confirming the receipt, should switch over the sda line to the low status. of course, there should be considered the pre - set time and the hold time. the ?master? device should signalize on completion of the data transfer to the slave device, ceasing gene ration of the confirmation bit on receiving the receipt confirmation from the slave cycle pulse. in this case, the ?slave one should switch over the data line to the low status, in order to enable the ?master? one generate the condition of stop.
i n1307 10 2013, dece m ber , ver.0 4 data tr ansfer by the serial two - wire bus depending on the status of bit , there are possible two types of transfer: 1. data are transferred from the ?master? transmitter to the ?slave? receiver. the first byte, transmitted by the ?master? one, is the address for the ?slave? one. then follows a sequence of the data bytes. the ?slave? one returns the receipt confirmation bytes after each received byte. order of the data transfer: the first is the most senior digit (msb). 2. the data are tran sferred from the ?slave? transmitter to the ?master? receiver. the first byte (address of ?slave?) is applied to the ?master?. then the ?master? returns the confirmation bit. this follows after the transfer by the ?slave? of the data sequence. the ?master? returns the receipt confirmation bit after each received byte, with the exception of the last byte. after receipt of the last byte the receipt confirmation bit is not returned. the ?master? device generates all cycle pulses and the statuses start and stop . transfer is completed at emergence of the status stop or the repeated emergence of the status start. as the repeated status start is the beginning of the next serial transfer, the bus is not vacated.the data transfer order: the first is the most senior d igit (msb). w r /
i n1307 11 2013, dece m ber , ver.0 4 IN1307 can operate in the two following modes 1. mode of ?slave? receiver (write mode of IN1307): serial data and cycles are received via sda and scl appropriately. after transfer of each byte the confirmation bit is sent. the statuses start and stop are recognized as the beginning and the end of the serial transfer. the address recognition is performe d by means of the hardware after receipt of the slave address and the direction bit. the address byte isthe first byte, received after occurrence of the start status, generated by the master. the address byte contains the seven address bits of IN1307, equal to 1101000, accompanied by the direction bit ( ), which for write is equal to 0.after receipt and decoding of the address byte, ds1307 applies confirmation to the line sda. after confirmation by IN1307 of the slave address and the write bit, the ?master? sends the register address of IN1307. thus the register indicator will be preset in IN1307. then the ?smart? shall start to send each data byte with the subsequent receipt confirmation of each byte. upon completion of writing th e master shall formulate the status stop for termination of the data transfer. d ata writing - mode of << slave>> receiver d ata writing - m ode of << slave>> receiver w r / s - s t a r t a - a c k n o w l e d g e p - s t o p * r / w - r e a d / w r i t e o r d i r e c t i o n b i t a d d r e s s = d 0 h d a t a t r a n s f e r r e d ( x + 1 b y t e s + a c k n o w l e d g e ) s s 1 1 0 1 0 0 0 1 1 0 1 0 0 0 0 0 a a x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x a a x x x x x x x x x x x x x x x x a a x x x x x x x x x x x x x x x x a a a a p p < s l a v e a d d r e s s > < r / w > < w o r d a d d r e s s ( n ) > < d a t a ( n ) > < d a t a ( n + 1 ) > < d a t a ( n + x ) >
i n1307 12 2013, dece m ber , ver.0 4 2. mode of ?slave? tran ceiver ( read - out mode from IN1307): the first byte is received and processed as in the mode of the ?slave? receiver. however, in this mode the direction bit will signify, that the transmission direction is changed. IN1307 sends the s e- rial data by sda, the cycle pulses - by scl. st atuses start and stop are understood as the b e- ginning and end of the consecutive transmission. the address byte is the first byte, received after occurrence of the status start, generated by the ?master?. the address byte contains the seven bits of the add ress IN1307, equal to 1101000, accompanied by the direction bit ( ), which is equal to 1 for reading. after receipt and decoding of the address byte IN1307 receives confirmation from the line sda. then IN1307 starts to send the data fr om the address, which is indicated by the register indicator. if the register indicator is not written prior to initialization of the read mode, then the first read address is the last address , retained in the register indicator. IN1307 should send the bi t of ?non - confirmation?, in order to complete the reading. d ata reading C mode of << slave>> transmitter master reads after setting word address (write word address ; read data ) data reading C mode of ?slave? transmitter w r / s s l a v e _ a d d r e s s 0 a w o r d _ a d d r e s s a s s l a v e _ a d d r e s s 1 a d a t a a 1 p d a t a r / w r / w a c k n o w l e d g e m e n t f r o m s l a v e a c k n o w l e d g e m e n t f r o m s l a v e a c k n o w l e d g e m e n t f r o m s l a v e a c k n o w l e d g e m e n t f r o m m a s t e r a u t o i n c r e m e n t m e m o r y w o r d a d d r e s s a t t h i s m o m e n t m a s t e r - t r a n s m i t t e r b e c o m e s m a s t e r r e c e i v e r a n d i n 1 3 6 3 s l a v e - r e c e i v e r b e c o m e s s l a v e - t r a n s m i t t e r n b y t e a u t o i n c r e m e n t m e m o r y w o r d a d d r e s s l a s t b y t e n o a c k n o w l e d g e m e n t f r o m m a s t e r s s 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 1 a a x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x a a x x x x x x x x x x x x x x x x a a x x x x x x x x x x x x x x x x a a a a p p < s l a v e a d d r e s s > < r / w > < d a t a ( n ) > < d a t a ( n + 1 ) > < d a t a ( n + 2 ) > < d a t a ( n + x ) > s - s t a r t a - a c k n o w l e d g e p - s t o p a - n o t a c k n o w l e d g e * r / w - r e a d / w r i t e o r d i r e c t i o n b i t a d d r e s s = d 1 h d a t a t r a n s f e r r e d ( x + 1 b y t e s + a c k n o w l e d g e ) : l a s t d a t a b y t e i s f o l l o w e d b y a n o t a c k n o w l e d g e ( a ) s i g n a l
i n1307 13 2013, dece m ber , ver.0 4 application note crystal considerations with real - time clocks (rtcs) this application note describes crystal selection and layout techniques for connecting a 32,768hz crystal to a real - time (rtc). it also provides information about oscillator circuit - design criteria, system design, and man u- facturing issue. oscillator basi cs the oscillator used in rtcs is a cmos inverter variation of a pierce - type oscillator. figure 1 shows a ge n- eral configuration. these rtcs include integrated load capacitors (cl1 and cl2) and bias resistors. the pierce oscillator utilizes a crystal oper ating in parallel - resonance mode. crystals used in parallel - resonance mode will be specified for a certal frequency with a specific load capacitance. for the oscillator to run at the correct frequency, the oscillator circuit must load crystal with the corr ect capacitive load. figure 1. rtc oscillator with internal load capacitors and bias resistors. accuracy the frequency accuracy of a crystal - based oscillator circuit is mainly dependent upon the accuracy of the crystal and the accuracy of the match between the crystal and the oscillator capacitive load. if the capacitive load is less than the crystal was desi gned for, the oscillator runs fast. if the capacitive load is greater than what the crystal was designed for, the oscillator runs slow. in addition to the errors from the crystal and the load match, crystals vary from their base frequency as the ambient temperature changes. rtcs use "tuning fork" crystals, which exhibit an error over temperature, as shown in figure 2 . an error of 20ppm is equivalent to approximately 1 minute per month.
i n1307 14 2013, dece m ber , ver.0 4 figure 2. crystal frequency vs. temperature. note: if better accuracy is required, a tcxo such as the ds32khz can be used crystal parameters figure 3 shows the equivalent circuit for a crystal. near the resonate frequency the circuit consists of a s e- ries circuit including motional inductance l1, motional resistance r1, and motional capacitance c1. the pa r- allel component c o is the shunt capacitance of the crystal. figure 3. crystal equivalent circuit. the load capacitance cl is the capacitive load of the oscillating circuit as seen from the pins of the crystal. figure 4 shows cl as a capacitance in parallel with the crystal. the load capacitors used in an oscillator circuit, cl1 and cl2, plus any stray capacitance in the circuit, combine to create the overall load capacitance. all rtcs have integrated cl1 and cl2 capacitors. care should be taken to minimize stray capacitance in the pc board layout. the following formula shows the relationship b etween cl and load capacitor values:
i n1307 15 2013, dece m ber , ver.0 4 figure 4. crystal load capacitors and equivalent parallel load. most crystals allow a maximum drive level of 1w. all rtcs run under 1w. drive level may be determined using the following formula: oscillator startup time oscillator startup times are highly dependent upon crystal characteristics, pc board leakage, and layout. high esr and excessive capacitive loads are the major contributors to long startup times. a circuit using a crystal with the recommended characteristics and proper layout usually starts within one second. table 1. crystal specifications parameter symbol min typ max units nominal frequency f o 32.768 khz frequency tolerance delta f/ f o 20 ppm load capacitance c l 6 pf temperature turnover point t 0 20 25 30 c parabolic curvature constant k 0.042 ppm/c quality factor q 40,000 70,000 series resistance esr 45 k ? shunt capacitance c 0 1.1 1.8 pf capacitance ratio c 0 /c 1 430 600 drive level d l 1 w note 1: some devices allow higher esr values, check the datasheet for specific requirements.
i n1307 16 2013, dece m ber , ver.0 4 table 2. crystal suppliers, cylinder - type (esr=45 k ? note: cylinder - type dimensions are barrel diameter and length, and exclude leads. all dimensions approximate. table 3. crystal suppliers, surface mount manufacturer links http://www.citizen.co.jp/tokuhan/quartz/catalog1/crystals.htm http://www.eea.epson.com/ http://www.kdsj.co.jp/english.html http://www.pletronics.com/xtal.htm#32 http://www.foxonline.com/ http://www.ecsxtal.com/thrucrys.htm
i n1307 17 2013, dece m ber , ver.0 4 power consumption many rtcs are designed to operate from a battery supply. in a typical application, a small l ithium ba t- tery can be used to run the oscillator and clock circuitry while the main supply is off. to maximize battery life, the oscillator must run using as little power as possible. to accomplish this, some design tradeoffs must be made. negative resist ance for typical high - frequency oscillator circuits, it is normal for the circuit to be designed with a 5 or 10x margin for the esr. low - frequency crystals typically have higher esrs. an rtc oscillator may have less than a 2x margin for negative resistance. an oscillator circuit with a low margin normally consumes less cu r- rent. as a result, an rtc oscillator often is sensitive to relatively small amounts of stray leakage, noise, or an increase in esr. the cl of the oscillator circuit influences th e power consumption. an rtc with 12.5pf i n- ternal loads consumes more power than one that has 6pf loads. however, the oscillator with 12.5pf load capacitors is usually less susceptible to noise. crystal layout guidelines since the crystal inputs of rtcs have very high impedance (about 109 ), the leads to the crystal act like very good antenna, coupling high - frequency signals from the rest of the system. if a signal is coupled onto the crystal pins, it can either cancel out or add pulses. since most of the signals on a board are at a much higher frequency than the 32.768khz crystal, it is more likely to add pulses where none are wanted. these noise pulses get counted as extra clock "ticks" and make the clock appear to run fa st. the following steps illustrate how to determine if noise is causing the rtc to run fast: 1. power the system up and synchronize the rtc to a known accurate clock. 2. turn the system power off. 3. wait for a period of time (two hours, 24 hours, etc.). the longer the time period, the easier it is to measure the accuracy of the clock. 4. turn the system on again, read clock, and compare to the known accurate clock. 5. resynchronize the rtc to the known accurate clock. 6. keep the system powered up and wait for a pe riod of time equal to the period in step 3. 7. read the clock after waiting for the above period of time and compare it to the known accurate clock. by using the above steps, the accuracy of the clock can be determined both when the system is po w- ered up an d when the system is powered down. if the clock proves to be inaccurate when the system is powered up, but is accurate when the system is powered down, the problem is most likely due to noise from other signals in the system. however, if the clock is ina ccurate both when the system is powered up and when it is powered down, then the problem is not due to noise from the system. since it is possible for noise to be coupled onto the crystal pins, care must be taken when placing the external crystal on a pc b oard layout. it is very important to follow a few basic layout guidelines concerning the placement of the crystal on the pc board layout to e n- sure the extra clock ticks do not couple onto the crystal pins. 1. it is important to place the crystal as close as possible to the x1 and x2 pins. keeping the trace lengths between the crystal and rtc as small as possible reduces the probability of noise coupling by reducing the length of the antenna. keeping the trace lengths small also decreases the amount of stray capacitance. 2. keep the crystal bond pads and trace width to the x1 and x2 pins as small as possible. the larger these bond pads and traces are, the more likely it is that noise can couple from adjacent signals.
i n1307 18 2013, dece m ber , ver.0 4 3. if possible, place a guard ring (connected t o ground) around the crystal. this helps isolate the crystal from noise coupled from adjacent signals. see figure 2 for an illustration of using a guard ring around a crystal. 4. try to ensure that no signals on other pc board layers run directly below the c rystal or below the traces to the x1 and x2 pins. the more the crystal is isolated from other signals on the board, the less likely it is that noise is coupled into the crystal. there should be a minimum of 0.200 inches b e- tween any digital signal and any t race connected to x1 or x2. the rtc should be isolated from any component that generates electromagnetic radiation (emr). this is true for discrete and module type rtcs. 5. it may also be helpful to place a local ground plane on the pc board layer immediatel y below the crystal. this helps to isolate the crystal from noise coupling from signals on other pc board layers. note that the ground plane needs to be in the vicinity of the crystal only and not on the entire board. see figure 5 for an illustration of a local ground plane. note that the perimeter of the ground plane does not need to be larger than the outer perimeter of the guard ring. note that care must be taken concerning the use of a local ground plane because of the stray capac i- tance that it introduces. the capacitance between the traces/pads and ground plane is added to the internal load capacitors (c l 1 and c l 2). therefore, some factors must be taken into account when considering adding a local ground plane. for example, the capacitance due t o the ground plane can be approximated by the following equation: therefore, to determine if a ground plane is appropriate for a given design, the above parameters must be taken into account to ensure that the capacitance from the local ground plane is not sufficiently large enough to slow down the clock. figure 5. recommended layout for crystal. checking for oscillation the first impulse that a designer has when checking for oscillator operation often is to connect an o s- ci l loscope probe to the oscillator input (x1) or output (x2) pin. doing so is not recommende d when using a real - time clock. since the oscillator is designed to run at low power (which extends operating time from a battery), loading the oscillator with an oscilloscope probe is likely to stop the oscillator. if the oscillator does not stop, the add itional loading will reduce the signal amplitude, and may cause erratic operation, such as varying amplitude. oscillation should therefore be verified indirectly.
i n1307 19 2013, dece m ber , ver.0 4 oscillation can be verified several ways. one method is to read the seconds register multip le times, looking for the data to increment. on rtcs with an osf (oscillator stop flag), clearing and then monitoring this bit will verify that the oscillator has started and is continuously running. these methods wont work if the designer is troubleshoot ing a design and cannot communicate with the rtc. an alternate method is to check the square wave output on rtcs that have a square wave output. check the datasheet to verify if the rtc must be written first to enable the oscillator and square wave output. note that most rtc square wave ou t- puts are open - drain, and require a pull up resistor for operation. the square wave output can also be used to verify the accuracy of the rtc, however, a frequency counter with sufficient accuracy must be used. fast clock s the following are the most common scenarios that cause a crystal - based rtc to run fast. 1. noise coupling into the crystal from adjacent signals. this problem has been extensively covered above. noise coupling usually causes an rtc to be grossly inaccurate. 2. wrong crystal. an rtc typically runs fast if a crystal with a specified load capacitance (cl) greater than the rtc - specified load capacitance is used. the severity of the inaccuracy is dependent on the value of the cl. for example, using a crystal with a cl of 12pf on an rtc designed with a 6pf cl causes the rtc to be about 3 to 4 minutes per month fast. slow clocks the following are the most common scenarios that cause a crystal - based rtc to run slow. 1. overshoots on rtc input pins. it is possible to cause a rtc to run slow by periodically stopping the oscillator. this can be inadvertently accomplished by noisy input signals to the rtc. if an input si g- nal rises to a voltage that is greater than a diode drop (~0.3v) above vdd, the esd protection diode for the input pin will forward bias, allowing the substrate to be flooded with current. this , in turn, stops the oscillator until the input signal voltage decreases to below a diode drop above vdd. this mechanism can cause the oscillator to stop frequently if input signals are noisy. therefore, care should be taken to ensure there is no overshoot on input signals. another situation that is common to overshoot problem is having an input to the rtc a t 5v when the rtc is in battery - backup mode. this can be a problem in systems that systematically shut down ce r- tain circuits but keep others powered up. it is very important to ensure there are no input signals to the rtc that are greater than the battery voltage (unless stated otherwise in the device data sheet) when the device is in battery - backup mode. 2. wrong crystal. a rtc typically runs slow if a crystal with a specified cl is less than the cl of the rtc. the severity of the inaccuracy is dependent on the value of the cl. 3. stray capacitance. stray capacitance between the crystal pins and/or to ground can slow an rtc down. therefore, care must be taken when designing the pc board layout to ensure the stray c a- pacitance is kept to a minimum. 4. temperature. the further the operating temperature is from the crystal turnover temperature, the slower the crystal oscillates. see figures 3 and 4. clock does not run the following are the most common scenarios that cause a rtc to not run. 1. the single most common problem when the clock does not run is that the ch (clock halt) or eosc (enable oscillator) bit has not been set or cleared, as required. many rtcs include a circuit that keeps the oscillator from running when power is first applied. this allows a s ystem to wait for shi p- ment to the customer, without drawing power from the backup battery. when the system is powered for the first time, the software/firmware must enable the oscillator and prompt the user for the correct time and date. 2. surface mount crys tals may have some n.c. (no connect) pins. make sure that the correct pins from the crystal are connected to the x1 and x2 pins.
i n1307 20 2013, dece m ber , ver.0 4 crystal manufacturing issues tuning fork crystals should not be exposed to ultrasonic cleaning. they are susceptible to d amage from resonant vibration. crystals should not be exposed to temperatures above their maximum ratings. exposure to excessive temperatures may damage the crystal, and usually increase the esr. crystal "cans" should not be soldered to a pc board. this is sometimes done to ground the case of the crystal. soldering directly to the case of the crystal usually subjects the unit to excessive temperatures. rtcs should generally be used in noncondensing environments. moisture forming around the oscill a- tor co nductors can cause leakage, which can cause the oscillator to stop. conformal coatings can be used to protect the circuit, however, conformal coating may by itself cause problems. some conformal coatings, especially epoxy - based materials, can have unacce ptable levels of ionic contamination. in addition, conformal coatings can, if the pc board surface is not sufficiently cleaned prior to conformal coating, cause contaminants to concentrate around leads and traces. solder flux residue can cause leakage be tween pins. rtc oscillator circuits are especially sensitive to leakage because of their low - power operation. leakage between the oscillator input and output, or leakage to ground, often keep the oscillator from running. typical application circuit
i n1307 21 2013, dece m ber , ver.0 4 package dimension n suffix plastic dip (ms C 001ba) symbol min max a 8.51 10.16 b 6.1 7.11 c 5.33 d 0.36 0.56 f 1.14 1.78 g h j 0 10 k 2.92 3.81 notes: l 7.62 8.26 1. ???? dimensions a, b do not include mold flash or protrusions. m 0.2 0.36 maximum mold flash or protrusions 0.25?mm (0.010) per side. n 0.38 dimension, mm 2.54 7.62 l h m j a b f g d seating plane n k 0.25 (0.010) m t -t- c 1 8 4 5
i n1307 22 2013, dece m ber , ver.0 4 n suffix plastic dip (ms C 001ba) symbol min max a 8.51 10.16 b 6.1 7.11 c 5.33 d 0.36 0.56 f 1.14 1.78 g h j 0 10 k 2.92 3.81 notes: l 7.62 8.26 1. ???? dimensions a, b do not include mold flash or protrusions. m 0.2 0.36 maximum mold flash or protrusions 0.25?mm (0.010) per side. n 0.38 d suffix soic (ms - 012aa) symbol min max a 4.8 5 b 3.8 4 c 1.35 1.75 d 0.33 0.51 f 0.4 1.27 g h j 0 8 notes: k 0.1 0.25 1. ???? dimensions a and b do not include mold flash or protrusion. m 0.19 0.25 2. ???? maximum mold flash or protrusion 0.15?mm (0.006) per side p 5.8 6.2 for a; for b ? 0.25?mm (0.010) per side. r 0.25 0.5 1.27 5.72 dimension, mm dimension, mm 2.54 7.62 a b h c k c m j f m p g d r x 45 seating plane 0.25 (0.010) m t -t- 1 8 4 5 l h m j a b f g d seating plane n k 0.25 (0.010) m t -t- c 1 8 4 5
i n1307 23 2013, dece m ber , ver.0 4 test fixture for in1363 & IN1307 application note ik semicon
i n1307 24 2013, dece m ber , ver.0 4 contents 1. test fixture overview ................................ ................................ ................................ ................................ . 25 1.1. installing the hardware ................................ ................................ ................................ ..................... 25 1.2. major components ................................ ................................ ................................ .......................... 25 1.3. basic specification ................................ ................................ ................................ .......................... 27 2. real time clock program ................................ ................................ ................................ .......................... 28 2.1. flow chart ................................ ................................ ................................ ................................ ..... 28 2.2.1. initializ ation register setting up ................................ ................................ ................................ .... 30 2.2.2 timer register setting up ................................ ................................ ................................ ............... 30 2.3 register set up for IN1307 ................................ ................................ ................................ ............... 31 2.3.1. initialization register setting up ................................ ................................ ................................ .... 31 2.3.2 timer register setting up ................................ ................................ ................................ ............... 31 2.4 hyper terminal configuration ................................ ................................ ................................ ........... 32 3. example source for rtc ................................ ................................ ................................ ........................... 34 3.1. read current time from in1363 & IN1307 ................................ ................................ ........................ 34 3.2.write set time for in1363 & IN1307 ................................ ................................ ................................ . 34 3.3. i2c example source for in1363 & IN1307 ................................ ................................ ........................ 35 4. test procedure for rtc ................................ ................................ ................................ ............................. 38 4.1. test procedure for in1363 ................................ ................................ ................................ ................ 38 4. 2. test procedure for IN1307 ................................ ................................ ................................ ................ 38
i n1307 25 2013, dece m ber , ver.0 4 1. test fixture overview in order to supply convenient method for rtc test , ik - semicon prepared test fixture. it s controlled by silabs mcu c8051f410 , user can rtc test by using this fixture. 1.1. installing the hardware in1363 /IN1307 is an ic compatible real time clock (rtc). as an application example, it demonstrates how to setup the rtc . this application note e xplain how to set the register value into a date and time value that can be put in the following form [yy]:[ mm] :[ dd ]: [ hh ]:[ mm] :[ ss]. 1.2. major components f ig 1. test board schematic
i n1307 26 2013, dece m ber , ver.0 4 fig 2 top view of test fixture fig 3 layout of test fixture . socket rs232c socket and pcb should be aligned in the same direction. adapter (main power ? 2 4 0 0 m a polarity + polarity - initial switch programming writing connector s i l a b s c 8 0 5 1 f 4 1 0 r s 2 3 2 c m a x 3 2 2 3 e l e d i n 1 3 0 7 i n 1 3 6 3 i n 1 3 0 7 s o c k e t i n 1 3 0 7 s o c k e t 3 2 . 7 6 8 k h z 3 2 . 7 6 8 k h z t p 1 t p 2 t p 3 t p 4 t p 5 t p 6 t p 7 t p 8 t p 1 1 t p 1 2 t p 1 3 t p 1 4 t p 1 5 t p 1 6 t p 1 0 t p 9 a b c e f f h i j k d i n 1 3 6 3 s o c k e t i n 1 3 6 3 s o c k e t
i n1307 27 2013, dece m ber , ver.0 4 1.3. basic specification a. 12v dc - jack : power terminal this power terminal normally is connected to the 12v power supply. b. init switch this switch initialize time to 23 july 2012, current time to 14:03:02(in1363) . c. led this led blinking every 1 seconds. if there is a power on the test fixture. d. test point in/output pin of the mcu is connected. i f need the user, use as the test pin. e. debugger connector this test program exchanges with pc(personal computer) through this debugger connector. f. rs232c female connector user can see the test time through this connector. g. 32.768khz connection of the standard quartz resonator for the frequency 32.768khz. in1363 can operate from external oscillator with the frequency 32.768khz note : to oscillation the 32.768khz , reset to the bit test1 h. IN1307_bat if you test the IN1307, c onnect battery on the IN1307_bat. i. in1363_bat if you test the in1363, c onnect battery on the in1363_bat n ote: although the power el iminate , the real time clock is working if the battery is connected on the IN1307/in1363_bat j. in1363_socket to test of in1363 rtc, it should select in1363_socket. k. IN1307_socket to test of IN1307 rtc, it should select IN1307_socket. n ote: to avoid any co nfusion by program selector, only one ic should be selected by socket.
i n1307 28 2013, dece m ber , ver.0 4 2. real time clock program 2.1. flow chart fig 3. f low chart for in1363 p o w e r o n : i n 1 3 6 3 i n 1 3 6 3 i n i t i a l i z e w r i t e d a t a * b i t t e s t 1 = 0 s w p r e s s d t e : 9 6 0 0 b p s r t c d i s p l a y r e a d d a t a : a d d r e s s 0 x 0 0 y e s ( r e a d d a t a & 0 x 8 0 ) = = 0 n o r e a d d a t a : a d d r e s s f r o m 0 x 0 2 t o 0 x 8 n o y e s i n 1 3 6 3 i n i t i a l i z e w r i t e d a t a t e s t 1 b i t = 0 ; a d d r e s s , d a t a 0 x 0 2 , 0 x 0 2 a d d r e s s , d a t a 0 x 0 3 , 0 x 0 3 a d d r e s s , d a t a 0 x 0 4 , 0 x 1 4 a d d r e s s , d a t a 0 x 0 5 , 0 x 2 3 a d d r e s s , d a t a 0 x 0 7 , 0 x 0 7 a d d r e s s , d a t a 0 x 0 8 , 0 x 1 2 1 2 [ y y ] : 0 7 [ m m ] : 2 3 [ d d ] : 1 4 [ h h ] : 0 3 [ m m ] : 0 2 [ s s ] d t e : c o n t i n u e s t a r t a t 1 3 6 3 a c k r e c e i v e d y e s d t e : i n i t i a l i z e b y m e m o r y n o d a t a y e s d t e : i n i t i a l i z e b y s w p r e s s y e s i n 1 3 6 3 i n i t i a l i z e w r i t e d a t a d t e : i 2 c e r r o r n o a c k n o a c k r e c e i v e d n o d t e : r t c n o a c k i n r e a d y e s
i n1307 29 2013, dece m ber , ver.0 4 fig 4. f low chart for IN1307 p o w e r o n : i n 1 3 0 7 i n 1 3 0 7 i n i t i a l i z e w r i t e d a t a * b i t c h = 0 s w p r e s s d t e : 9 6 0 0 b p s r t c d i s p l a y r e a d d a t a : a d d r e s s 0 x 0 0 y e s ( r e a d d a t a & 0 x 8 0 ) = = 0 n o r e a d d a t a : a d d r e s s f r o m 0 x 0 0 t o 0 x 0 6 n o y e s d t e : c o n t i n u e s t a r t a t 1 3 0 7 a c k r e c e i v e d y e s d t e : i n i t i a l i z e b y m e m o r y n o d a t a y e s d t e : i n i t i a l i z e b y s w p r e s s y e s i n 1 3 0 7 i n i t i a l i z e w r i t e d a t a d t e : i 2 c e r r o r n o a c k n o a c k r e c e i v e d n o d t e : r t c n o a c k i n r e a d y e s i n 1 3 0 7 i n i t i a l i z e w r i t e d a t a c h b i t = 0 ; a d d r e s s , d a t a 0 x 0 0 , 0 x 0 5 a d d r e s s , d a t a 0 x 0 1 , 0 x 1 0 a d d r e s s , d a t a 0 x 0 2 , 0 x 1 3 a d d r e s s , d a t a 0 x 0 3 , 0 x 0 5 a d d r e s s , d a t a 0 x 0 4 , 0 x 1 5 a d d r e s s , d a t a 0 x 0 5 , 0 x 0 6 a d d r e s s , d a t a 0 x 0 6 , 0 x 1 2 a d d r e s s , d a t a 0 x 0 7 , 0 x 0 0 1 2 [ y y ] : 0 6 [ m m ] : 1 5 [ d d ] : 5 [ d a y ] : 1 3 [ h h ] : 1 0 [ m m ] : 5 [ s s ]
i n1307 30 2013, dece m ber , ver.0 4 2.2. register set up for in1363 2.2.1. initialization register setting up it is necessary to enable the generation (bit test1 = 0) when setting the initial configurations . . register a d- dress register name initialize write data contents 0x00h control/status 1 0x00 test1 bit = 0 (normal mode) stop bit = 0 (rtc source clock) testc bit = 0 (normal op) 0x01h control/status 2 0x00 aie bit = 0 (alarm int disabled) tie bit = 0 (timer int disabled) 0x0dh clkput control - 0x0eh timer control - 0x0fh timer - 2.2.2 timer register setting up register a d- dress register name initialize write data contents 0x02h seconds 0x02 0x03h minutes 0x03 0x04h hours 0x14 0x05h dates 0x23 0x06h day of week - sunday=0,monday=1,tuesday=2, wednesday=3,..., saturday=6 0x07h century/month 0x07 bit7 c of the months/century register indicates century for year 19xx (bit7=1), and year 20xx (bit7=0). 0x08h year 0x12 0x09h minute alarm - 0x0ah hour alarm - 0x0bh date alarm - 0x0ch weekday alarm for example, we want to set the date for 23 july 2012, current time to 12:03:02, and then we need to call. 1. seconds setup : rtc_write( seconds, 0x02); 2. minutes setup : rtc_write( minutes, 0x03); 3. hours setup : rtc_write( hours, 0x14); 4. dates setup : rtc_write( dates, 0x23); 5. month setup : rtc_write( month, 0x07); 6. year setup : rtc_write( year, 0x12);
i n1307 31 2013, dece m ber , ver.0 4 2.3 register set up for IN1307 2.3.1. initialization register setting up it is necessary to enable the generation (bit ch = 0) when setting the initial configurations . . register a d- dress register name initialize write data contents 0x00h.bit8 control/status 1 0x00 ch bit = 0 (normal mode) 2.3.2 timer register setting up register a d- dress register name initialize write data contents 0x00h seconds 0x05 0x01h minutes 0x10 0x02h hours 0x13 0x03h day 0x05 range 1 - 7 0x04h date 0x15 0x05h month 0x06 0x06h year 0x12 0x07h control for example, we want to set the date for 23 june 2012, current time to 13:10:05, and then we need to call. 1. seconds setup : rtc_write( 0x00 , 0x0 5 ); 2. minutes setup : rtc_write( 0x01, 0x10); 3. hours setup : rtc_write( 0x02, 0x13); 4. day setup : rtc_write( 0x03, 0x05); 5. dates setup : rtc_write( 0x04, 0x15); 6. month setup : rtc_write( 0x05, 0x06); 7. year setup : rtc_write (0x06 , 0x12);
i n1307 32 2013, dece m ber , ver.0 4 2.4 hyper terminal configuration 1. bits per second : 9600 bps 2. data bit : 8 bit 3. parity bit : none 4. s top bits : 1 bit 5. flow control : none fig 5. e xample test p rogram for in1363 run the serial terminal and make sure the baud rate is set correctly at 9600bps fig 6 . in1363 rtc data on serial terminal
i n1307 33 2013, dece m ber , ver.0 4 fig 7 . IN1307 rtc data on serial terminal
i n1307 34 2013, dece m ber , ver.0 4 3. example source for rtc this documentation shows an example of a main function to setup and read/write data. i f you request example source code, we can provide source codes. 3.1. read current time from in1363 & IN1307 ? slave address of in1363 = 0xa2 ? slave address of IN1307 = 0xd0; 3.2.write set time for in1363 & IN1307
i n1307 35 2013, dece m ber , ver.0 4 3.3. i2c example source for in1363 & IN1307 #ifdef in1363 sbit scl = p 1 ^ 7 ; sbit sda = p 1 ^ 6 ; // #endif #ifdef IN1307 sbit sda = p0^2; sbit scl = p0^1; #endif void i2c_start(void) / / start condition { sda = high; delaytimeloop(); scl = high; delaytimeloop(); sda = low; delaytimeloop(); scl = low; delaytimeloop(); } void i2c_stop(void) // stop condition { scl = high; delaytimeloop(); s da = high; delaytimeloop(); } /* clock pulse generation. the function returns data or acknowledgment bit */ unsigned char i2c_clock(void)//bit i2c_clock(void) { bit level; // state of sda line scl = 1; delaytimeloop(); while (!scl); // if a pulse was stretched delaytimeloop(); level = sda; delaytimeloop(); scl = 0; return (level); } /* writing a byte to a slave, with most significant bit first. the function returns acknowledgment bit.*/ unsigned char i2c_write(unsigned char byte ) { unsigned char mask = 0x80; unsigned char aaa; while (mask) { if (byte & mask)
i n1307 36 2013, dece m ber , ver.0 4 sda = 1; else sda = 0; i2c_clock(); mask >>= 1; } aaa = i2c_clock(); return (aaa); } /* reading byte from a slave, with most significant bit first. the parameter indicates, whether to acknowledge (1) or not (0) */ unsigned char i2c_read(unsigned char acknowledgment) { uchar mask = 0x80, byte = 0x00; while (mask) { if (i2c_clock()) byte |= mask; mask >>= 1; /* next bit to receive */ } if (ac knowledgment) { sda = 0; i2c_clock(); sda = 1; } else { sda = 1; i2c_clock(); } return (byte); } unsigned char rtc_read_7_byte(unsigned char addr) { unsigned char status , i; i2c_start(); if (!i2c_write( 0xa2 )){ //0xa2 is slave address for in1363, 0xd2 is for IN1307 delaytimeloop(); if (!i2c_write(addr)){ i2c_start(); if (!i2c_write( 0xa2 | 0x01)){ IN1307 s slave address is 0xd2 for(i=0;i<6;i++){ receive_data[i] = i2c_read(1); } receive _data[6] = i2c_read(0); } else { status = 1; } } else{ status = 1;
i n1307 37 2013, dece m ber , ver.0 4 } } else status = 1; i2c_stop(); return(status); }
i n1307 38 2013, dece m ber , ver.0 4 4. test procedure for rtc 4.1. test procedure for in1363 1. make sure that test fixture is power off. 2. place in1363 on in1363_socket of test fixture. 3. connect the battery on in1363_bat. 4. run the serial terminal and make sure the baud rate is set correctly at 9600bps 5. after turning on the power of test fixture, identify whether green led of status indicator is flickering. if that s flickering every 1s, it indicates in1363 working . method for the program is refer to the chapter 2. 6. data is displayed in serial terminal window like to fig6. refer to fig 6 7. and then test fixture is power off. 8. wa it for a period of time ( two hours, 10 minutes, etc .). 9. turn the test fixture on again, and check the time. the amount time as power off is passed . 4.2. test procedure for IN1307 1. make sure that test fixture is power off. 2. place in1363 on IN1307_socket of test fixture. 3. connect the battery on IN1307_bat. 4. run the serial terminal and make sure the baud rate is set correctly at 9600bps 5. after turning on the power of test fixture, identify whether green led of status indicator is flickering. if that s flicker ing every 1s, it indicates IN1307 working . method for the program is refer to the chapter 2. 6. data is displayed in serial terminal window like to fig7. refer to fig 7 7. and then test fixture is power off. 8. wait for a period of time ( two hours, 10 minutes, etc .). 9. turn the test fixture on again, and check the time. the amount time as power off is passed .

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